The introduction of copper as a metallization material in integrated circuits, i.e., for forming corresponding contact locations and/or contact pads and/or rewirings during microchip fabrication, has brought with it a number of changes to the process technology used in the various wiring planes. The method which is customarily used at present for the fabrication of copper tracks is what is known as the “damascene” technology. Unlike when patterning metal layers by dry-etching processes, in this technology the trench and contact hole structures are firstly transferred into the insulator and then filled with the desired metal, usually copper. For this deposition process, an electrochemical deposition, i.e., electroplating, is preferred, on account of the better filling properties and on account of its microstructural and electrical advantages. However, for electroplating of this type, an electrically conductive base metallization (seed layer) must first be applied to the corresponding substrate. The resistivity and the morphology of the base metallization determine the properties of the copper layer which is subsequently electrochemically deposited in order to form corresponding contact locations and/or contact pads and/or rewirings. To improve the bonding and to prevent copper from diffusing into the insulator, with resulting transistor failures, it is necessary to construct a barrier layer between the base metallization and the insulator (for example silicon dioxide or dielectrics with a lower dielectric constant).
Barrier layer and base metallization are usually produced in two independent steps by means of physical vapor deposition or chemical vapor deposition (CVD). Special physical or chemical vapor deposition processes have been developed for the deposition of, for example, copper base metallizations which have to be homogenous and free of defects. However, a general problem encountered with CVD methods for metal deposition is that the deposited metal layers contain certain amounts of foreign atoms (i.e., precursor impurities). This leads to an undesirable increase in the resistivity of the base metallization.
Moreover, ever decreasing feature sizes mean that it is necessary to reduce the layer thicknesses of all the metal layers as part of the fabrication of integrated electronic components or microchips of this type. However, in terms of the process development and optimization, this generally entails high levels of outlay. In addition, smaller feature sizes and therefore higher aspect ratios (trench height to trench width) give rise to further problems, such as for example incomplete side wall coverage in sputtering processes. Deposition of thin metal layers which are just a few metal atomic layers thick is a possible but very expensive technique for future technology generations.
One method of solving the above-described problems is, for example, to introduce a further process step, in which an inhomogeneous base metallization is optimized (seed repair). However, an additional process step of this type is always expensive.